MicroVAX

The MicroVAX was a family of low-cost minicomputers developed and manufactured by Digital Equipment Corporation (DEC). The first model, the MicroVAX I, was introduced in 1984. The MicroVAX family used processors that implemented the VAX instruction set architecture (ISA) and was succeeded by the VAX 4000.

The MicroVAX I, code named "Seahorse", introduced in October 1984, was one of DEC's first VAX computers to use very-large-scale integration (VLSI) technology. The KA610 CPU module (also known as the KD32) contained two custom chips which implemented the ALU and FPU while TTLs were used for everything else. Two variants of the floating point chips were supported, with the chips differing by the type of floating point instructions supported, F and G, or F and D.

The MicroVAX II, code named "Mayflower", was a mid-range MicroVAX introduced in May 1985. It ran VAX/VMS or, alternatively, ULTRIX, the DEC native Unix operating system.

It used the KA630-AA CPU module, a quad-height Q22-Bus module, which featured a MicroVAX 78032 microprocessor and a MicroVAX 78132 floating-point coprocessor operating at 5 MHz (200 ns cycle time). Two gate arrays on the module implemented the external interface for the microprocessor, Q22-bus interface and the scatter-gather map for DMA transfers over the Q22-Bus. The module also contained 1 MB of memory, an interval timer, two ROMs for the boot and diagnostic facility, a DZ console serial line unit and a time-of-year clock. A 50-pin connector for a ribbon cable near the top left corner of the module provided the means by which more memory was added to the system.

The MicroVAX II supported 1 to 16 MB of memory through zero, one or two memory expansion modules. The MS630 memory expansion module was used for expanding memory capacity. Four variants of the MS630 existed: the 1 MB MS630-AA, 2 MB MS630-BA, 4 MB MS630-BB and the 16MB MS630-CA. The MS630-AA was a dual-height module, whereas the MS630-BA, MS630-BB and MS630-CA were quad-height modules. These modules used 256 Kb DRAMs and were protected by byte-parity, with the parity logic located on the module. The modules connected to the CPU module via the backplane through the C and D rows and a 50-conductor ribbon cable. The backplane served as the address bus and the ribbon cable as the data bus.

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