Memory ordering

Memory ordering describes the order of accesses to computer memory by a CPU. The term can refer either to the memory ordering generated by the compiler during compile time, or to the memory ordering generated by a CPU during runtime.

In modern microprocessors, memory ordering characterizes the CPUs ability to reorder memory operations - it is a type of out-of-order execution. Memory reordering can be used to fully utilize the bus-bandwidth of different types of memory such as caches and memory banks.

On most modern uniprocessors memory operations are not executed in the order specified by the program code. In single threaded programs all operations appear to have been executed in the order specified, with all out-of-order execution hidden to the programmer – however in multi-threaded environments (or when interfacing with other hardware via memory buses) this can lead to problems. To avoid problems memory barriers can be used in these cases.

The compiler has some freedom to sort the order of operations during compile time. However this can lead to problems if the order of memory accesses is of importance.

These barriers prevent a compiler from reordering instructions during compile time – they do not prevent reordering by CPU during runtime.

or even

forbids GCC compiler to reorder read and write commands around it.

forbids the compiler to reorder read and write commands around it.

intrinsics.

There are several memory-consistency models for SMP systems:

On some CPUs

Some older x86 and AMD systems have weaker memory ordering

SPARC memory ordering modes:

Many architectures with SMP support have special hardware instruction for flushing reads and writes during runtime.

Some compilers support builtins that emit hardware memory barrier instructions:

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