Logic analyser

A logic analyzer is an electronic instrument that captures and displays multiple signals from a digital system or digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces, assembly language, or may correlate assembly with source-level software. Logic Analyzers have advanced triggering capabilities, and are useful when a user needs to see the timing relationships between many signals in a digital system.

Presently, there are three distinct categories of logic analyzers available on the market:

A logic analyzer can be triggered on a complicated sequence of digital events, then capture a large amount of digital data from the system under test (SUT).

When logic analyzers first came into use, it was common to attach several hundred "clips" to a digital system. Later, specialized connectors came into use. The evolution of logic analyzer probes has led to a common footprint that multiple vendors support, which provides added freedom to end users. Introduced in April, 2002, connectorless technology (identified by several vendor-specific trade names: Compression Probing; Soft Touch; D-Max) has become popular. These probes provide a durable, reliable mechanical and electrical connection between the probe and the circuit board with less than 0.5 to 0.7 pF loading per signal.

Once the probes are connected, the user programs the analyzer with the names of each signal, and can group several signals together for easier manipulation. Next, a capture mode is chosen, either "timing" mode, where the input signals are sampled at regular intervals based on an internal or external clock source, or "state" mode, where one or more of the signals are defined as "clocks", and data are taken on the rising or falling edges of these clocks, optionally using other signals to qualify these clocks.

After the mode is chosen, a trigger condition must be set. A trigger condition can range from simple (such as triggering on a rising or falling edge of a single signal) to the very complex (such as configuring the analyzer to decode the higher levels of the TCP/IP stack and triggering on a certain HTTP packet).

At this point, the user sets the analyzer to "run" mode, either triggering once, or repeatedly triggering.

Once the data are captured, they can be displayed several ways, from the simple (showing waveforms or state listings) to the complex (showing decoded Ethernet protocol traffic). Some analyzers can also operate in a "compare" mode, where they compare each captured data set to a previously recorded data set, and halt capture or visually notify the operator when this data set is either matched or not. This is useful for long-term empirical testing. Recent analyzers can even be set to email a copy of the test data to the engineer on a successful trigger.

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