Load Program Status Word instruction

System/360

Designer	IBM
Bits	32-bit
Introduced	1964; 54 years ago (1964)
Design	CISC
Type	Register-Register Register-Memory Memory-Memory
Encoding	Variable (2, 4 or 6 bytes long)
Branching	Condition code, indexing, counting
Endianness	Big
Page size	N/A, except for 360/67
Open	Yes
Registers
General purpose	16× 32-bit
Floating point	4× 64-bit

IBM S/360 registers

63 . . . 47 . . . 31 . . . 15 . . . 00 (bit position)* General-purpose registers 0 R0 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 9 R9 10 R10 11 R11 12 R12 13 R13 14 R14 15 R15 Floating-point registers FP0 FP0 FP2 FP2 FP4 FP4 FP6 FP6 Program status word / Instruction address PSW (40 bits) IA (24 bits) Program Status Word  * Note that IBM documentation numbers the bits in reverse order to that shown    above, i.e., the most significant (leftmost) bit is designated as bit number 0.

The IBM System/360 architecture is the model independent architecture for the entire S/360 line of mainframe computers, including but not limited to the instruction set architecture. The elements of the architecture are documented in the IBM System/360 Principles of Operation and the IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information manuals.

 * Note that IBM documentation numbers the bits in reverse order to that shown
   above, i.e., the most significant (leftmost) bit is designated as bit number 0.

The System/360 architecture provides the following features:

Memory (storage) in System/360 is addressed in terms of 8-bit bytes. Various instructions operate on larger units called halfword (2 bytes), fullword (4 bytes), doubleword (8 bytes), quad word (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as big-endian. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term word refers to a fullword.

The original architecture of System/360 provided for up to 2²⁴ = 16,777,216 bytes of memory. The later Model 67 extended the architecture to allow up to 2³² = 4,294,967,296 bytes of virtual memory.

System/360 uses truncated addressing. That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15 general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.

The S/360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Character and integer instructions are mandatory, but decimal and floating point instructions are part of the Decimal arithmetic and Floating-point arithmetic features.

Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats:

Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0.

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