LatticeMico32
| Designer | Lattice Semiconductor |
|---|---|
| Bits | 32-bit |
| Introduced | 2006 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed 32-bit |
| Branching | Compare and branch |
| Endianness | Big |
| Extensions | User-defined |
| Open | Yes |
| Registers | |
| General purpose | 32 |
LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.
LatticeMico32 is licensed under a free (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture (FPGA, ASIC, or software emulation (e.g. QEMU)). It is possible to embed a LatticeMico32 core into Xilinx and Altera FPGAs, in addition to the Lattice parts the LatticeMico32 was developed for. AMD PowerTune is using LatticeMico32.
Both the CPU core and the development toolchain are available in source-code form, allowing third parties to implement changes to the processor architecture.
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