Korg Poly-61
| Poly-61 | |
|---|---|
Poly-61
|
|
| Manufacturer | Korg (Keio Electronic Laboratories) |
| Dates | 1982-1986 |
| Technical specifications | |
| Polyphony | 6 voices |
| Timbrality | Monotimbral |
| Oscillator | 2 DCOs per voice |
| LFO | 1 |
| Synthesis type | Analog Subtractive |
| Filter | 1 low-pass per voice |
| Attenuator | 1 VCA per voice 1 ADSR envelope per voice |
| Storage memory | 64 patches |
| Input/output | |
| Keyboard | 61 keys |
| External control | Poly-61M has MIDI |
The KORG Poly-61 is a programmable polyphonic synthesizer released by Korg in 1982, as a successor to the Polysix. It was notable for being Korg's first "knobless" synthesizer - featuring a push-button interface for programming, dispensing from the Polysix's knobs and switches. The Poly-61 also moved to a hybrid tone-generation system, using digitally controlled analog oscillators or DCO's (Roland's Juno-6 had made the same leap the previous year), in place of the Polysix' more retrograde VCOs.
In 1984 a MIDI version, the Poly-61M was released featuring basic MIDI implementation.
The Poly-61 offers two DCOs per voice. DCO1 provides sawtooth, pulse, and PWM waveforms. DCO2 has only sawtooth and square.
The filter has the typical controls for cutoff, resonance, keyboard tracking and envelope amount. Some of these are rather limited by the poor parameter resolution. Keyboard tracking is simply "on" or "off" for example, and resonance and envelope level (here labelled "EG Intensity") have only 8 values.
The final component in the audio path is a VCA. It can be driven by the envelope generator or a CV/Gate pulse.
NEC D8049C - 8 bits, 11 MHz (max.), 40 pins (DIP), Supply Voltage = 5V
There are 2 of them on the CPU board (KLM-509), one is a Programmer and the other is an Assigner.
The 8049 has 2 kB of masked ROM as well as 128 bytes of RAM and 27 I/O ports. The µC's oscillator block divides the incoming clock into 15 internal phases, thus with its 11 MHz max. crystal, one gets 0.73 MIPS (of one-clock instructions). Some 70% of instructions are single byte/cycle, but 30% need two cycles and/or two bytes, so raw performance is closer to 0.5 MIPS. The minimum instruction length is 8 bits and the maximum instruction length is 16 bits.
The envelope is an ADSR type. All parameters can only be set to one of 16 values.
...
Wikipedia