Intel 8237

Intel 8237 is a direct memory access (DMA) controller, a part of the MCS 85 microprocessor family. It enables data transfer between memory and the I/O with reduced load on the system's main processor by providing the memory with control signals and memory address information during the DMA transfer.

The 8237 is a four-channel device that can be expanded to include any number of DMA channel inputs. The 8237 is capable of DMA transfers at rates of up to 1.6 MByte per second. Each channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k bytes with a single programming.

A single 8237 was used as the DMA controller in the original IBM PC and IBM XT. The IBM PC AT added another 8237 in master-slave configuration, increasing the number of DMA channels from four to seven. Later IBM-compatible personal computers may have chip sets that emulate the functions of the 8237 for backward compatibility.

The 8237 operates in four different modes, depending upon the number of bytes transferred per cycle and number of ICs used:

Memory-to-memory transfer can be performed. This means data can be transferred from one memory device to another memory device. The channel 0 Current Address register is the source for the data transfer and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.

In auto initialize mode the address and count values are restored upon reception of an end of process (EOP) signal. This happens without any CPU intervention. It is used to repeat the last transfer.

The terminal count (TC) signals end of transfer to ISA cards. At the end of transfer an auto initialize will occur configured to do so.

In single mode only one byte is transferred per request. For every transfer, the counting register is decremented and address is incremented or decremented depending on programming. When the counting register reaches zero, the terminal count TC signal is sent to the card.

The DMA request DREQ must be raised by the card and held active until it is acknowledged by the DMA acknowledge DACK.

The transfer is activated by the DREQ which can be deactivated once acknowledged by DACK. The transfer continues until end of process EOP (either internal or external) is activated which will trigger terminal count TC to the card. Auto-initialization may be programmed in this mode.

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