IBM 8000

The IBM 8000 series was a proposed transistor-based successor to the IBM 7000 series. Important engineers on the project included Fred Brooks and Gerry Blaauw. The project plan for the 8000 series was presented by Fred Brooks in January, 1961. Despite some technical successes, the project became a political football, amid IBM's search for a unified product line. The project was canceled in 1961 by Bob Evans, supplanted by the successful System/360 series.

The 8000 project may have seen the first use of the term "architecture" in relation to computers.

Pugh cites a number of reasons for the cancellation of the 8000 line.

Unlike System/360 which offered a series of processors with a common architecture, the 8000 was designed with a single main processor to which external components could be added to increase performance.

The components identified were:

The 8103 was proposed as a low-end processor "to relieve the larger systems of the series from the tasks associated with input-output processing." The 8103 was to have featured a 4 K or 8 K 8 μs magnetic-core memory, organized as 16 bit words of two eight bit bytes. The system could also share 2 μs core memory with larger processors. Memory was organized into segments — segment size is unspecified in the proposal. The 8103 was to be multiprogrammed to support its mission as an input/output or front end processor. Interestingly it appears that task switching was to be automatic under hardware control.

The proposed specifications for the 8104 appear similar to the 8103. It featured a full complement of instructions for fixed and floating point arithmetic and storage-to-storage character operations. All instructions were 32 bits in length. The 8104 supported direct addressing, indirect addressing, and indexed addressing with 255 index registers.

The 8106 was to have been the principal processor in the 8000 line, designed to bracket the performance of the IBM 7090 system. The 8106 used a 64 bit word in one or more storage units of 4 K, 8 K, or 16 K words of core memory with an access time of 2 μs. Some of the storage units were supposed to be able to have been shared with other processors in the product line. Instructions could be one, two, or three 32-bit halfwords in length, allowing one, two, or three address instructions respectively. The system used nonpaged virtual memory, addressing blocks of 256 words through an address translation table.

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