Honeywell 316
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| Type | 16-bit minicomputer |
|---|---|
| Release date | 1969 |
| Memory | 4K to 32K words, magnetic-core |
The Honeywell 316 was a popular 16-bit minicomputer built by Honeywell starting in 1969. It is part of the Series 16, which includes the Models 116, 316, 416, 516 and 716. They were commonly used for data acquisition and control, remote message concentration, clinical laboratory systems and time-sharing. The Series-16 computers are all based on the DDP-116 designed by Gardner Hendrie at Computer Control Company, Inc. (3C) in 1964.
The H-316 was used by Charles H. Moore to develop the first complete, stand-alone implementation of Forth at NRAO. They were used as ARPANET Interface Message Processors (IMP) but could also be configured as a Terminal IMP (TIP), which added support for up to 63 teletype machines through a multi-line controller.
The original Prime computers were designed to be compatible with the Series-16 minicomputers.
The Honeywell 316 also had industrial applications. A 316 was used at Bradwell nuclear power station in Essex as the primary reactor temperature-monitoring computer until summer 2000, when the internal 160k disk failed. Two PDP-11/70s, which had previously been secondary monitors, were moved to primary.
The 316 succeeded the earlier DDP-516 model and was promoted by Honeywell as suitable for industrial process control, data-acquisition systems, and as a communications concentrator and processor. The computer processor was made from small-scale integration DTL monolithic integrated circuits. Most parts of the system operated at 2.5 MHz, but some elements were clocked at 5 MHz. The computer was a bitwise-parallel 2's complement system with 16-bit word length. The instruction set was a single-address type with an index register. Initially released with a capacity of 4096 through 16,384 words of memory, later expansion options allowed increasing memory space to 32,768 words. Memory cycle time was 1.6 microseconds; an integer register-to-register "add" instruction took 3.2 microseconds. An optional hardware arithmetic option was available to implement integer multiply and divide, double-precision load and store, and double-precision (31-bit) integer addition and subtraction operations. It also provided a normalization operation, assisting implementation of software floating-point operations.
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