HP-48 series
HP 48GX
|
|
| Type |
Programmable Scientific Graphing |
|---|---|
| Manufacturer | Hewlett-Packard |
| Introduced | 1990 |
| Discontinued | 2003 |
| Predecessor | HP-28S |
| Successor | HP 49G |
| Cost | 350 USD |
| Calculator | |
| Entry mode | RPN |
| Precision | 12 BCD digits, exp ±499 |
| Display type | LCD |
| Display size | 131×64 pixels |
| CPU | |
| Processor | Yorke (Saturn 1LT8 core) |
| Frequency | 2-4 MHz |
| Programming | |
| Programming language(s) | RPL / Machine language |
| User memory | 128 KB |
| Firmware memory | 512 KB |
| External memory | Port 1 128 KB Port 2 4,096 KB |
| Interfaces | |
| Connection | 4-pin RS-232, HP-IR |
| Ports | Serial: |
| Other | |
| Power supply | 4.5 V (3× AAA battery) |
| Weight | 0.25 kg (0.55 lb) |
| Dimensions | 17.9×7.9×2.8 cm (7.05×3.11×1.1 inch) |
The HP 48 is a series of graphing calculators using Reverse Polish Notation (RPN) and the RPL programming language, produced by Hewlett-Packard from 1990 until 2003. The series include the HP 48S, HP 48SX, HP 48G, HP 48GX, and HP 48G+, the G models being expanded and improved versions of the S models. The models with an X suffix are expandable via special RAM (memory expansion) and ROM (software application) cards. In particular, the GX models have more onboard memory than the G models. The G+ models have more onboard memory only. The SX and S models have the same amount of onboard memory.
Note that the similarly named hp 48gII (2004) is not really a member of the series, but rather much more closely related to the hp 49g+.
The hardware architecture developed for the HP 48 series became the basis for the HP 38G, with a simplified user interface and an infix input method, and the HP 49G with various software enhancements. Likewise, the hardware and software design of the HP 48 calculators are themselves strongly influenced by other calculators in the HP line, most of all by the HP-18C and the HP-28 series.
The HP 48SX was introduced on 1990-03-06.
Availability:
The HP 48 series' Saturn microprocessor is a hybrid 64-bit / 20-bit CPU hardware-wise but acts like a 4-bit processor in that it presents nibble-based data to programs and uses a nibble-based addressing system. The main registers A, B, C, D, along with temp registers R0, R1, R2, R3, and R4 are a full 64-bits wide, but the data registers D0 & D1 are only 20-bit. External logical data fetches are transparently converted to 8-bit physical fetches. The processor has a 20-bit address bus available to code but due to the presence of the high/low nibble selection bit, only 19 bits are available externally.
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