HCS12
| Designer | Freescale Semiconductor |
|---|---|
| Bits | 8-bit/16-bit |
| Design | CISC |
| Encoding | Variable |
| Endianness | Big |
| Registers | |
| 8 | |
The 68HC12 (6812 or HC12 for short) is a microcontroller family from Freescale Semiconductor. Originally introduced in the mid-1990s, the architecture is an enhancement of the Freescale 68HC11. Programs written for the HC11 are usually compatible with the HC12, which has a few extra instructions. The first 68HC12 derivatives had a maximum bus speed of 8 MHz and flash memory sizes up to 128 KB.
Like the 68HC11, the 68HC12 has two 8-bit accumulators A and B (referred to as a single 16-bit accumulator, D, when A & B are cascaded so as to allow for operations involving 16 bits), two 16-bit registers X and Y, a 16-bit program counter, a 16-bit stack pointer and an 8-bit Condition Code Register. Unlike the 68HC11 the processor has 16bit internal data paths
The 68HC12 adds to and replaces a small number of 68HC11 instructions with new forms that are closer to the 6809 processor. More significantly it changes the instruction encodings to be far more dense and adds many 6809 like indexing features, some with even more flexibility. The net result is that code sizes are typically 30% smaller.
Beginning in 2000 the family was extended with the introduction of the MC9S12 derivatives which have bus speeds of up to 25 MHz and flash sizes up to 512 KB.
The MC9S12NE64 was introduced by Freescale in September 2004, claiming to be the "industry's first single-chip fast-Ethernet Flash microcontroller." It features a 25 MHz HCS12 CPU, 64 KB of FLASH EEPROM, 8 KB of RAM, and an Ethernet 10/100 Mbit/s controller.
The MC9S12XDP512 which was introduced in 2004 has a bus speed of 40 MHz and a peripheral co-processor known as the XGATE which allows for some tasks to be offloaded from the CPU. The CPU of the S12X derivative also features several new instructions to increase performance.
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