Freescale RS08

The RS08 [1] core is a reduced-resource version of the Freescale MC68HCS08 central processing unit (CPU), a member of the 6800 microprocessor family. It has been implemented in several microcontroller devices for embedded systems.

Compared to its sibling HC08 and Freescale S08 parts, it has a much-simplified design. The 'R' in its part numbers suggests "Reduced"; Freescale itself describes the core as "ultra-low-end". Typical implementations include fewer on-board peripherals and memory resources, have smaller packages (the smallest is the QFN6 package, at 3mm x 3mm x 1mm), and are priced under US $1. Aims of the simplified design include greater efficiency, greater cost-effectiveness for small-memory-size parts, and smaller die size.

The RS08 employs a von Neumann architecture with shared program and data bus; executing instructions from within data memory is possible. The device is not binary compatible with the S08 core, though the instruction opcodes and addressing modes are a subset of the S08. This allows an easy transition from the S08 core to the RS08 core for designers and engineers.

Short and Tiny addressing modes allow for more efficient access and manipulation of the most-commonly-used variables and registers. These instructions have single-byte instruction opcodes, reducing the amount of program memory required by their frequent use.

Die size is 30% smaller than the S08 core. The RS08 core uses the same bus structure as S08, making memory and peripheral module reuse possible. It offers a Background Debug Mode interface, a single-wire debugging interface that allows interactive control over the processor when installed in a target system.

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