Fairchild F8
F3850, the CPU of the Fairchild F8 system.
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| Produced | 1975 |
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| Common manufacturer(s) | |
| Max. CPU clock rate | ? MHz to 1.79 MHz |
| Instruction set | 8-bit |
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The Fairchild F8 was an 8-bit microprocessor system created by Fairchild Semiconductor announced in 1974, shipped in 1975.
The engineers who designed the Fairchild F8 Microcomputer did so mindful of a set of goals. The computer needed to be electrically frugal. It needed characteristics that permitted easy interface to standard SSI and MSI components. It needed a moderate instruction set. It needed to be easy to incorporate into a design. The design needed to put the maximum number of computer components and circuits into the LSI components to minimize the package count. This approach reduced the time spent on designing support logic circuits.
These goals resulted in a microcomputer with a multiplexed bus architecture, with just two buses for all functions: the time-multiplexed data bus and a 7-bit control bus for synchronizing the system's components relative to the data bus. The functions of the F8 were distributed among several devices resulting in system simplification.
In the F8 the control bus regulates the use of the data bus through the use of timing signals and state controls. The phi clock divides the machine cycle into discrete phases depending on the instruction being executed. The five state control lines are a function of the instruction being executed. The control bus states regulate the control of information in the computer.
The F3851 is the program storage unit containing 1K ROM. It is programmed in manufacturing using a mask that could be specified by the customer of Fairchild. The F3851A PSU, in the F8 Evaluation Kit 1, was filled with the Fairbug program that allowed inspection and modification of memory, jumping to routines, viewing registers, punching paper tape, and interacting with a teletype user. All 64K of memory could be addressed, and any section could be RAM or ROM. The Fairbug PSU was a demonstration of packing many routines into a 1K ROM.
The program counter (PC) is maintained in the F3851 PSU. There is one program counter for each PSU in the system. Each PSU has a backup program counter. The PSU also contains a pointer register called a data counter, DC. The user only sees one program counter and one data counter.
There are no restrictions in the F8 for how memory addresses are used. They can be either for program or data. Memory interaction has the feature of a Turing machine allowing the computer to put operands in memory and then use the operands as operators.
The F8 has two bidirectional 8-bit ports built into every PSU. An interrupt in the F3850 is similar to a subroutine call. A power-on detection organizes the computer circuitry.
The machine instructions can be grouped into six categories: accumulator instructions, branch instructions, memory reference instructions, address register instructions, scratchpad register instruction, miscellaneous instructions (interrupt, input, output, indirect scratchpad register, load, and store).
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