FPGA prototype

FPGA prototyping, sometimes also referred to as FPGA-based prototyping, ASIC prototyping, or SoC prototyping, is the method to prototype SoC and ASIC design on FPGA for hardware verification and early software development.

Verification methods for hardware design as well as early software and firmware co-design have become mainstream. Prototyping SoC and ASIC design with one or more FPGAs has become a good method to do this.

Many of the obstacles facing development teams who adopt FPGA prototypes can be distilled down to three "laws":

Putting a SoC design into an FPGA prototype requires careful planning in order to accomplish prototyping goals with minimal effort. To ease the development of the prototype, best practices called, Design-for-Prototyping (or DFP), influences both the SoC design style and the project procedures applied by design teams. Procedural recommendations include adding DFP conventions to RTL coding standards, employing a prototype compatible simulation environment, and instituting a system debug strategy jointly with the software team.

Due to increased circuit complexity, and time-to-market shrinking, the need for verification of application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) designs is growing. Hardware platforms are becoming more prominent amongst verification engineers due to the ability to test system designs at-speed with on-chip bus clocks, as compared to simulation clocks which may not provide an accurate reading of system behavior. These multi-million gate designs usually are placed in a multi-FPGA prototyping platform with six or more FPGAs, since they are unable to fit entirely onto a single FPGA. The fewer number of FPGAs the design has to be partitioned to reduces the effort from the design engineer. To the right is a picture of a FPGA-based prototyping platform utilizing a dual-FPGA configuration.

System RTL designs or netlist’s will have to be partitioned onto each FPGA to be able to fit the design onto the prototyping platform. This introduces new challenges for the engineer since manual partitioning requires tremendous effort and frequently results in poor speed (of the design under test). If the number or partitions can be reduced or the entire design can be placed onto a single FPGA, the implementation of the design onto the prototyping platform becomes easier.

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Wikipedia