Designer | IBM |
---|---|
Bits | 64-bit |
Introduced | 2000 |
Version | ARCHLVL 2 and ARCHLVL 3 (2008) |
Design | CISC |
Type | Register-Memory Memory-Memory |
Encoding | Variable (2, 4 or 6 bytes long) |
Branching | Condition code, indexing, counting |
Endianness | Big |
Registers | |
General purpose | 16× 64-bit |
Floating point | 16× 64-bit (plus 32× 128-bit vector registers in latest version) |
z/Architecture, initially and briefly called ESA Modal Extensions (ESAME), is IBM's 64-bit instruction set architecture implemented by its mainframe computers. IBM introduced its first z/Architecture-based system, the z900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890, System z9, System z10, zEnterprise 196, and zEnterprise 114. z/Architecture retains backward compatibility with previous 32-bit-data/31-bit-addressing architecture ESA/390 and its predecessors all the way back to the 32-bit-data/24-bit-addressing System/360.
Each z/OS address space, called a 64-bit address space, is 16 exabytes in size. A z/OS address space is 8 billion times the size of the former 2-gigabyte address space.
Most operating systems, including z/OS, generally restrict code execution to the first 2 GB (31 address bits, or 231 addressable bytes) of each virtual address space for reasons of efficiency and compatibility rather than because of architectural limits. The z/OS implementation of the Java programming language is an exception. The z/OS's virtual memory implementation supports multiple 2 GB address spaces, permitting more than 2 GB of concurrently resident program code. The 64-bit version of Linux on System z allows code to execute within 64-bit address ranges.