Dadda multiplier

The Dadda multiplier is a hardware multiplier design invented by computer scientist Luigi Dadda in 1965. It is similar to the Wallace multiplier, but it is slightly faster (for all operand sizes) and requires fewer gates (for all but the smallest operand sizes).[1]

In fact, Dadda and Wallace multipliers have the same 3 steps for two bit strings ${\displaystyle w_{1}}$ and ${\displaystyle w_{2}}$ of lengths ${\displaystyle l_{1}}$ and ${\displaystyle l_{2}}$ respectively:

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