DEC Firefly

The Firefly was a shared memory asymmetric multiprocessor workstation, developed by the Systems Research Center, a research organization within Digital Equipment Corporation. The first version built contained up to seven MicroVAX 78032 microprocessors. The cache from each of the microprocessors kept a consistent view of the same main memory using a cache coherency algorithm, the . The second version of the Firefly used faster CVAX 78034 microprocessors. It was later introduced as a product by DEC as VAX-3520/3540 and called 'Firefox'.

The Firefly was an asymmetric multiprocessor specialized racked computer as only one of the microprocessors had access to a Q-Bus interface that implemented the I/O subsystem.

The Firefly contained a primary processor board and zero, one, two or three secondary processor boards. These processor boards were 8 by 10 inches large. The primary processor board contained a microprocessor, its floating-point coprocessor and cache, and the Q-Bus control logic. The secondary processor boards each contained two microprocessors, their floating-point coprocessors and caches. The original Firefly processor boards used the MicroVAX 78032 microprocessor and MicroVAX 78132 floating-point coprocessor, but later Firefly systems used the faster CVAX 78034 microprocessors, CVAX Floating Point Chips (floating-point coprocessors). The processor boards communicated with each other and the memory via the MBus. The components used in the processor boards of the original Firefly were the same as those originally designed for the MicroVAX II system.

The caches in the Firefly were direct-mapped for simplicity and to support multiprocessing; they used the to ensure cache coherency. The caches on the MicroVAX processor boards had a capacity of 16 KB (4,096 4-byte lines) and were implemented with eleven 2 KB (4-bit by 4,096-word) SRAMs and twenty transistor–transistor logic (TTL) devices. The cache control logic was implemented with fifteen devices, mostly consisting of programmable array logic (PAL) devices. The caches on CVAX processor boards differed only in the capacity: 64 KB (16,384 4-byte lines) and were implemented with 8 KB (4-bit by 16,384-word) SRAMs.

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