Cray X-MP

Cray X-MP

The CERN CRAY-XMP48 displayed at the EPFL in Switzerland.
Manufacturer	Cray Research
Type	Supercomputer
Release date	1982 (1982)
Predecessor	Cray-1

The Cray X-MP is a supercomputer designed, built and sold by Cray Research. It was announced in 1982 as the "cleaned up" successor to the 1975 Cray-1, and was the world's fastest computer from 1983 to 1985. The principal designer was Steve Chen.

The X-MP's main improvement over the Cray-1 was that it was a shared-memory parallel vector processor, the first such computer from Cray Research. It housed two CPUs in a mainframe that was nearly identical in outside appearance to the Cray-1.

The X-MP CPU had a faster 9.5 nanosecond clock cycle (105 MHz), compared to 12.5 ns for the Cray-1A. It was built from bipolar gate-array integrated circuits containing 16 emitter-coupled logic gates each. The CPU was very similar to the Cray-1 CPU in architecture, but had better memory bandwidth (with two read ports and one write port to the main memory instead of only one read/write port) and improved chaining support. Each CPU had a theoretical peak performance of 200 MFLOPS, for a peak system performance of 400 MFLOPS.

The X-MP initially supported 2 million 64-bit words (16 MB) of main memory in 16 banks, respectively. Memory bandwidth was significantly improved over the Cray-1—instead of one port for both reads and writes, there were now two read ports, one write port, and one dedicated to I/O. The main memory was built from 4 Kbit bipolar SRAM ICs. CMOS memory versions of the Cray-1M were renamed Cray X-MP/1s. This configuration was first used for Cray Research's UNIX port.

In 1984, improved models of the X-MP were announced, consisting of one, two, and four-processor systems with 4 and 8 million word configurations. The top-end system was the X-MP/48, which contained four CPUs with a theoretical peak system performance of over 800 MFLOPS and 8 million words of memory. The CPUs in these models introduced vector gather/scatter memory reference instructions to the product line. The amount of main memory supported was increased to a maximum of 16 million words, depending on the model. The main memory was built from bipolar or MOS SRAM ICs, depending on the model.