Cortex-A57
| Designed by | ARM Holdings |
|---|---|
| Microarchitecture | ARMv8-A |
| Cores | 1–4 per cluster, multiple clusters |
| L1 cache | 80 KiB (48 KiB I-cache with parity, 32 KiB D-cache with ECC) per core |
| L2 cache | 512 KiB to 2 MiB |
| L3 cache | none |
The ARM Cortex-A57 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
In January 2014, AMD announced the Opteron A1100. Intended for servers, the A1100 has 4 or 8 Cortex-A57 cores, support for up to 128 GiB of DDR3 or DDR4 RAM, an 8-lane PCIe controller, 8 SATA (6 Gbit/s) ports, and two 10GigE ports. The A1100 series was released in January 2016, with four and eight core versions.
Qualcomm's first offering which was made available for sampling Q4 2014 was the Snapdragon 810. It contains four Cortex-A57 and four Cortex-A53 cores in a big.LITTLE configuration.
Samsung also provides Cortex-A57-based SoC's, the first one being Exynos Octa 5433 which was available for sampling from Q4 2014.
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