Compressed instructions

In computing, compressed instructions are a compact variation of the instruction set of a microprocessor aimed at increasing the code density of executable programs. They are a solution to the usual increased application binary sizes found on RISC architectures. Typically these machines have 32-bit instruction words, whilst the 'compressed mode' will have shortened 16-bit instructions, achieved via various compromises: only accessing a subset of the registers, more use of specific registers, and 2-operand arithmetic (rather than the usual 3-operand form found in RISC).

This strategy appeared first in the ARM architecture, where its use in mobile devices and embedded systems incentived such economies (some systems would have 16-bit external busses to reduce costs). It was later copied by other RISC vendors.

The Hitachi SH-4 architecture used 16-bit instructions from the outset, with a 16-entry register file and 2-operand instructions. CISC architectures such as the 68000 can have improved code density compared to RISC machines.

Code may also be compressed and decompressed by software, using arbitrary encodings.

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