Clocked logic

In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinatory logic circuits, particularly those implemented in MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs. Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate than static logic but the capacitative loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS or dynamic SOI design.

Dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed.

The static/dynamic terminology used to refer to combinatorial circuits should not be confused with how the same adjectives are used to distinguish memory devices, e.g. static RAM from dynamic RAM.

In the context of logic design, the term dynamic logic is more commonly used as compared to clocked logic, as it makes clear the distinction between this type of design and static logic. To additionally confuse the matter, clocked logic is sometimes used as a synonym for sequential logic. This usage is nonstandard and should be avoided.

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