CDC 924

CDC 1604 registers

⁴₇	. . .	¹₄	. . .	⁰₀	(bit position)
Operand registers (48 bits)
A					Accumulator
Q					Mask register
Program counter (15 bits)
		P			Program counter
Index registers (15 bits)
		1			Index 1
		2			Index 2
		3			Index 3
		4			Index 4
		5			Index 5
		6			Index 6

The CDC 1604 was a 48-bit computer designed and manufactured by Seymour Cray and his team at the Control Data Corporation (CDC). The 1604 is known as one of the first commercially successful transistorized computers. (The IBM 7090 was delivered in November 1959.) Legend has it that the 1604 designation was chosen by adding CDC's first street address (501 Park Avenue) to Cray's former project, the ERA-Univac 1103. A cut-down 24-bit version, designated the CDC 924, was also produced.

The first 1604 was delivered to the US Navy in 1960 for applications supporting major Fleet Operations Control Centers in Hawaii, London, and Norfolk, Virginia. By 1964, over 50 systems were built. The CDC 3000 succeeded the 1604.

A 12-bit minicomputer, called the CDC 160, was often used as an I/O processor in 1604 systems. A stand-alone version of the 160 called the CDC-160A was arguably the first minicomputer.

Memory in the CDC 1604 consisted of 32K 48-bit words of magnetic core memory with a cycle time of 6.4 microseconds. It was organized as two banks of 16K words each, with odd addresses in one bank and even addresses in the other. The two banks were phased 3.2 microseconds apart, so average effective memory access time was 4.8 microseconds. The computer executed about 100,000 operations per second.

Each 48-bit word contained two 24-bit instructions. The instruction format was 6-3-15: six bits for the operation code, three bits for a "designator" (index register for memory access instructions, condition for jump (branch) instructions) and fifteen bits for a memory address (or shift count, for shift instructions).

The CPU contained a 48-bit accumulator (A), a 48-bit mask register (Q), a 15-bit program counter (P), and six 15-bit index registers (1-6). Internal integer representation used one's complement arithmetic. Internal floating point format was 1-15-32: one bit of sign, fifteen bits of offset (biased) binary exponent, and thirty-two bits of binary mantissa.

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