Blackfin
| Designer | Analog Devices |
|---|---|
| Bits | 32-bit |
| Introduced | 2000 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Variable (16- or 32-bit general purpose, or 64-bit parallel issue of 1 × 32-bit instruction + 2 × 16-bit instructions) |
| Branching | Condition code |
| Endianness | Little |
| Registers | |
| General purpose | 8 × 32-bit data registers, 2 × 40-bit accumulators, 6 address registers, stack pointer, frame pointer |
ADI Blackfin Logo
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| Produced | From 2008 to Present |
|---|---|
| Marketed by | Analog Devices |
| Designed by | Analog Devices |
| Common manufacturer(s) | |
The Blackfin is a family of 16- or 32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit Multiply–accumulates (MACs), accompanied on-chip by a small microcontroller. It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding. There are several hardware development kits for the Blackfin. Open-source operating systems for the Blackfin include uClinux.
Blackfin processors use a 32-bit RISC microcontroller programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).
The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001.
It incorporates aspects of ADI's older SHARC architecture and Intel's XScale architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC architecture designs.
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