Arbiter (electronics)

Arbiters are electronic devices that allocate access to shared resources.

A bus arbiter is a device used in a multi-master bus system to decide which bus master will be allowed to control the bus for each bus cycle. The most common kind of bus arbiter is the memory arbiter in a system bus system.

A memory arbiter is a device used in a shared memory system to decide, for each memory cycle, which CPU will be allowed to access that shared memory.

Some atomic instructions depend on the arbiter to prevent other CPUs from reading memory "halfway through" atomic read-modify-write instructions.

A memory arbiter is typically integrated into the memory controller/DMA controller.

Some systems, such as Conventional PCI, have a single centralized bus arbitration device that one can point to as "the" bus arbiter. Other systems use decentralized bus arbitration, where all the devices cooperate to decide who goes next.

When every CPU connected to the memory arbiter has synchronized memory access cycles, the memory arbiter can be designed as a synchronous arbiter. Otherwise the memory arbiter must be designed as an asynchronous arbiter.

An important form of arbiter is used in asynchronous circuits to select the order of access to a shared resource among asynchronous requests. Its function is to prevent two operations from occurring at once when they should not. For example, in a computer that has multiple CPUs or other devices accessing computer memory, and has more than one clock, the possibility exists that requests from two unsynchronized sources could come in at nearly the same time. "Nearly" can be very close in time, in the sub-femtosecond range. The memory arbiter must then decide which request to service first. Unfortunately, it is not possible to do this in a fixed time [Anderson 1991].

Ivan Sutherland and Jo Ebergen, in their article "Computers without Clocks", describe Arbiters as follows:

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