Alliant Computer Systems

Alliant Computer Systems was a computer company that designed and manufactured parallel computing systems. Together with Pyramid Technology and Sequent Computer Systems, Alliant's machines pioneered the symmetric multiprocessing market. One of the more successful companies in the group, over 650 Alliant systems were produced over their lifetime. The company was hit by a series of financial problems and went bankrupt in 1992.

Alliant was founded, as Dataflow Systems, in May 1982 by Ron Gruner, Craig Mundie and Rich McAndrew to produce machines for scientific and engineering users who needed smaller, less costly machines than offerings from Cray Computer and similar high-end vendors. Machines that addressed this market segment later became known as minisupercomputers. At the time there was a huge gap on the price/performance curve as a highly configured VAX 11/780 had a performance of about a MIP and MegaFLOP for around $1M USD and a Cray-1S or Cray 1M over $10M USD.

Alliant's first machines were announced in 1985, starting with the FX series. The FX series consisted of four types of 18" x 18" boards: Computational Elements, or CEs, System Cache, Interactive Processor (IP) Cache, and Memory Modules. Each board plugged into a backplane using a special high density connector. The caches and memory modules all communicated with each other over a 2 x 64 bit bus called the DMB (Dataflow Memory Bus). The backplane was an active backplane and it contained an 8 x 4 crossbar switch (FX/8) that allowed any CE to connect to one of four cache ports, two on each System Cache. Total cache bandwidth was 376 MB/s.

The CEs included a set of Weitek 1064/1065 FPU's and several custom designed support chips to implement a custom vector processor. The scalar instruction set was based upon the popular Motorola 68000 architecture. The floating point instruction set, vector instruction set, and concurrency instruction set were all custom co-processor instruction sets designed by Alliant. The shared system cache and a special concurrency bus implemented low latency concurrency control that could be exploited automatically by high level language compilers to provide data-parallel processing among the CEs. Cycle time for the original CE was 170 ns.

...
Wikipedia