AVR32
| Designer | Atmel |
|---|---|
| Bits | 32-bit |
| Version | Rev 2 |
| Design | RISC |
| Encoding | Variable |
| Endianness | Big |
| Extensions | Java Virtual Machine |
| Registers | |
| 15 | |
The AVR32 is a 32-bit RISC microcontroller architecture produced by Atmel. The microcontroller architecture was designed by a handful of people educated at the Norwegian University of Science and Technology, including lead designer Øyvind Strøm, PhD and CPU architect Erik Renno, M.Sc in Atmel's Norwegian design center.
Most instructions are executed in a single-cycle. The multiply–accumulate unit can perform a 32-bit × 16-bit + 48-bit arithmetic operation in two cycles (result latency), issued once per cycle.
It does not resemble the 8-bit AVR, even though they were both designed at Atmel Norway, in Trondheim. Some of the debug-tools are similar.
The AVR32 has at least two micro-architectures, the AVR32A and AVR32B. These differ in the instruction set architecture, register configurations and the use of caches for instructions and data.
The AVR32A CPU cores are for inexpensive applications. They do not provide dedicated hardware registers for shadowing the register file, status and return address in interrupts. This saves chip area at the expense of slower interrupt-handling.
The AVR32B CPU cores are designed for fast interrupts. They have dedicated registers to hold these values for interrupts, exceptions and supervisor calls. The AVR32B cores also support a Java virtual machine in hardware.
The AVR32 instruction set has 16-bit (compact) and 32-bit (extended) instructions, similar to e.g. some ARM, with several specialized instructions not found in older ARMv5 or ARMv6 or MIPS32. Several U.S. patents are filed for the AVR32 ISA and design platform.
Just like the AVR 8-bit microcontroller architecture, the AVR32 was designed for high code density (packing much function in few instructions) and fast instructions with few clock cycles. Atmel used the independent benchmark consortium EEMBC to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (Thumb) code and ARMv5 32-bit (ARM) code by as much as 50% on code-size and 3× on performance.
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