ARM Cortex-A72
| Designed by | ARM Holdings |
|---|---|
| Microarchitecture | ARMv8-A |
| Cores | 1–4 per cluster, multiple clusters |
| L1 cache | 80 KiB (48 KiB I-cache with parity, 32 KiB D-cache with ECC) per core |
| L2 cache | 512 KiB to 4 MiB |
| L3 cache | none |
The ARM Cortex-A72 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A72 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
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