ARM9
| Designed by | ARM Holdings |
|---|---|
| Instruction set |
ARM (32-bit), Thumb (16-bit) |
| Microarchitecture | ARMv4T |
| Instruction set |
ARM (32-bit), Thumb (16-bit) |
|---|---|
| Microarchitecture | ARMv5TE |
| Instruction set |
ARM (32-bit), Thumb (16-bit), Jazelle (8-bit) |
|---|---|
| Microarchitecture | ARMv5TEJ |
ARM9 is a group of older 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. The cores were released from 1998 to 2006 and consisted of ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, ARM996HS.
With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed. Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories.
There are two subfamilies, implementing different ARM architecture versions.
Key improvements over ARM7 cores, enabled by spending more transistors, include:
Additionally, some ARM9 cores incorporate "Enhanced DSP" instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.
Switching to a Harvard architecture entailed a non-unified cache, so that instruction fetches do not evict data (and vice versa). ARM9 cores have separate data and address bus signals, which chip designers use in various ways. In most cases they connect at least part of the address space in von Neumann style, used for both instructions and data, usually to an AHB interconnect connecting to a DRAM interface and an External Bus Interface usable with NOR flash memory. Such hybrids are no longer pure Harvard architecture processors.
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