AArch32

ARM architectures
The ARM logo
Designer	ARM Holdings
Bits	32-bit, 64-bit
Introduced	1985; 32 years ago (1985)
Design	RISC
Type	Register-Register
Branching	Condition code, compare and branch
Open	Proprietary

64/32-bit architecture
Registers
Introduced	2011
Version	ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A
Encoding	AArch64/A64 and AArch32/A32 use 32-bit instructions, T32 (Thumb-2) uses mixed 16- and 32-bit instructions. ARMv7 user-space compatibility
Endianness	Bi (little as default)
Extensions	All mandatory: Thumb-2, NEON, Jazelle, VFPv4-D16, VFPv4
General purpose	31× 64-bit integer registers
Floating point	32× 128-bit registers for scalar 32- and 64-bit FP or SIMD FP or integer; or cryptography

32-bit architectures (Cortex)
Registers
Version	ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-M
Encoding	32-bit except Thumb-2 extensions use mixed 16- and 32-bit instructions.
Endianness	Bi (little as default); Cortex-M is fixed and can't change on the fly.
Extensions	Thumb-2, NEON, Jazelle, DSP, Saturated, FPv4-SP, FPv5
General purpose	15× 32-bit integer registers; R15 is PC (26-bit addressing in older), R14 is link register.
Floating point	Up to 32× 64-bit registers, SIMD/floating-point (optional)

32-bit architectures (legacy)
Registers
Version	ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
Encoding	32-bit except Thumb extension uses mixed 16- and 32-bit instructions.
Endianness	Bi (little as default) in ARMv3 and above
Extensions	Thumb, Jazelle
General purpose	15× 32-bit integer registers; R15 is PC (26-bit addressing in older), R14 is link register.

ARM, originally Acorn RISC Machine, later Advanced RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments. British company ARM Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures‍—‌including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products.

Processors that have a RISC architecture typically require fewer transistors than those with a complex instruction set computing (CISC) architecture (such as the x86 processors found in most personal computers), which improves cost, power consumption, and heat dissipation. These characteristics are desirable for light, portable, battery-powered devices‍—‌including smartphones, laptops and tablet computers, and other embedded systems. For supercomputers, which consume large amounts of electricity, ARM could also be a power-efficient solution.

ARM Holdings periodically releases updates to architectures and core designs. All of them support a 32-bit address space (only pre-ARMv3 chips, made before ARM Holdings was formed, as in original Acorn Archimedes, had smaller) and 32-bit arithmetic; instructions for ARM Holdings' cores have 32-bit fixed-length instructions, but later versions of the architecture also support a variable-length instruction set that provides both 32- and 16-bit instructions for improved code density. Some older cores can also provide hardware execution of Java bytecodes. The ARMv8-A architecture, announced in October 2011, adds support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.

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Wikipedia