10 nm

In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nanometer (10 nm) node as the technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nanometers.

Samsung first released their version of a "10 nm" process node in 2017.

The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm. Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, claimed in 2008 that Intel saw a 'clear way' towards the 10 nm node. At the 11 nm node, Intel expected (in 2006) to be using a half-pitch of around 21 nm, in 2015,Nvidia's chief scientist, William Dally, claimed (in 2009) that they would also reach 11 nm semiconductors in 2015, a transition he claimed would be facilitated principally through new electronic design automation tools.

As of 2014^[update], "10 nm" node was projected to use a metal pitch of 40–50 nm.

This 10 nm design rule is considered likely to be realized by multiple patterning, given the difficulty of implementing EUV lithography.

While the roadmap has been based on the continuing extension of CMOS technology, even this roadmap does not guarantee that silicon-based CMOS will extend that far. This is to be expected, since the gate length for this node may be smaller than 6 nm, and the corresponding gate dielectric thickness would scale down to a monolayer or even less. Scientists have estimated that transistors at these dimensions are significantly affected by quantum tunnelling. As a result, non-silicon extensions of CMOS, using III-V materials or carbon nanotube/nanowires, as well as non-CMOS platforms, including molecular electronics, spin-based computing, and single-electron devices, have been proposed. Hence, this node marks the practical beginning of nanoelectronics.

...
Wikipedia