• Engineering change order

    Engineering change order

    • Engineering change orders (ECO) are used for changes in components, assemblies, or documents such as processes and work instructions. They may also be used for changes in specifications.

      ECOs are also called an "engineering change note", engineering change notice (ECN), or just an engineering change (EC).

      In a typical system development cycle, the specification or the implementation is likely to change during engineering development or during integration of the system elements. These last-minute design changes are commonly referred to as engineering change orders (ECOs) and affect the functionality of a design after it has been wholly or partially completed. ECOs can compensate for design errors found during debug or changes that are made to the design specification to compensate for design problems in other areas of the system design.

      In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place, route, layout extraction, and timing verification. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.

      After masks have been made, ECOs may be done to save money. If a change can be implemented by modifying only a few of the layers (typically metal) then the cost is much less than it would be if the design was re-built from scratch. This is because starting the process from the beginning will almost always require new photomasks for all layers, and each of the 20 or so masks in a modern semiconductor fabrication process is quite expensive. A change implemented by modifying only a few layers is typically called a metal-mask ECO or a post-mask ECO. Designers often sprinkle a design with unused logic gates, and EDA tools have specialized commands, to make this process easier.

      One of the most common ECOs in ASIC design is the gate-level netlist ECO. In this flow, engineers manually (and often tediously) hand-edit the gate-level netlist, instead of re-running logic synthesis. The netlist files have to be searched for the logic affected by the change, the files need to be edited to implement the changes up and down the hierarchy, and the changes need to be tracked and verified to make sure exactly what needs to change gets changed and nothing more. This is a very time and resource-intensive process that is easily subject to errors. Therefore formal equivalence checking is normally used after ECOs to ensure the revised implementation matches the revised specification.

      • Correction of a design error that doesn't become evident until testing and modeling, or customer use reveals it.
      • A change in the customers' requirements necessitating the redesign of part of the product
      • A change in material or manufacturing method. This can be caused by a lack of material availability, a change in vendor, or to compensate for a design error.
      • Identification of what needs to be changed. This should include the part number and name of the component and reference to the drawings that show the component in detail or assembly.
      • Reason(s) for the change.
      • Description of the change. This includes a drawing of the component before and after the change. Generally, these drawings are only of the detail affected by the change.
      • List of documents and departments affected by the change. The most important part of making a change is to see that all pertinent groups are notified and all documents updated.
      • Approval of the change. As with the detail and assembly drawings, the changes must be approved by management.
      • Instruction about when to introduce the change—immediately (scrapping current inventory), during the next production run, or at some other milestone.
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    • Engineering change order